1. Field of the Invention
The present invention relates to a memory test circuit and method, and more specifically to a memory test circuit and method for testing plural memories.
2. Description of Related Art
In recent years, an LSI is becoming more sophisticated. Along with this, its configuration is complicated. In particular, there has been developed a technique of collectively integrating necessary functional blocks into one chip. This requires higher intelligence and more complicated configuration.
A requisite memory capacity increases as LSI attains higher intelligence. In this case, a memory may be provided outside the LSI but is desirably provided inside the LSI in consideration of the transfer time and physical size.
However, an embedded memory has a problem that a failure is more likely to occur, which largely influences a yield of the LSI. Therefore, a reliable operation test of a memory is required. However, a memory test circuit is complicated as an operation speed of the LSI increases or the LSI becomes more complicated, so a memory test method requires a larger number of steps.
To overcome this problem, there has been proposed a memory test method capable of reducing circuit scale and the requisite number of steps for operation test of an LSI having plural memory banks (for example, see Japanese Unexamined Patent Publication 2004-79032). The test method disclosed in this publication executes a command to simultaneously write data to identical addresses in respective banks, and executes a command to simultaneously read data from such addresses to determine whether or not the simultaneously read data coincide with an expected value in a data determination part, thereby checking the normality of a memory.
However, the method disclosed in this publication cannot test operations of memories which run at different operational clocks at actual operation speeds, due to the difference in operational clock. It is also impossible to test a memory at a physically remote location because a delay occurs. Thus, testing such a memory requires a special circuit such as a BIST (built-in self test) and costs high.